
PIC18F6585/8585/6680/8680
DS30491C-page 210
2004 Microchip Technology Inc.
FIGURE 17-13:
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SS
PI
F
BF
(
S
SPS
T
A
T
<
0
>
)
SSP
O
V
(
S
SPCO
N
<
6
>
)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
A
7
A6
A
5
A4
A
3
A2
A
1
D7
D6
D5
D4
D3
D
2
D1
D0
D7
D6
D5
D4
D3
D1
D0
ACK
Re
ce
ivin
g
Da
ta
ACK
Re
ce
ivin
g
Da
ta
R/W
=
0
ACK
R
e
cei
v
ing
A
ddr
ess
Cle
a
re
d
in
so
ft
wa
re
SSP
BUF
i
s
re
a
d
B
u
s
m
a
st
er
ter
m
inate
s
tra
n
sfer
S
SPO
V
is
s
e
t
becau
se
S
P
B
U
F
i
s
still
fu
ll.
ACK
is
n
o
tsent
.
D2
6
(P
IR
1<
3>
)
CK
P
CK
P
wr
itte
n
to
‘
1
’in
If
B
F
is
cleare
d
pr
ior
to
the
fa
llin
g
edg
e
of
t
he
9th
cl
ock,
CKP
will
n
o
tb
e
r
e
se
t
to
‘
0
’a
nd
no
cl
ock
str
e
tch
in
g
will
o
ccu
r
softwar
e
Clo
ck
is
h
e
ld
lo
w
u
n
til
CK
P
is
set
to
‘
1
’
Clo
ck
is
n
o
th
e
ld
lo
w
be
cause
b
u
ff
er
ful
lbi
ti
s
cl
ear
pr
io
rto
fal
ling
ed
ge
of
9th
cl
ock
C
lo
ck
i
s
not
hel
d
l
o
w
becau
se
A
C
K
=
1
BF
i
s
se
t
a
fte
r
fa
llin
g
e
dge
o
fthe
9
th
cl
ock,
CKP
is
r
e
se
tto
‘0
’a
n
d
clock
str
e
tch
ing
occu
rs